The present disclosure relates generally to circuits, and more specifically, but not exclusively, to executing computer instructions with memory arrays that have a reduced circuit design.
Computing devices can include any number of different types of memory to store data to be used by a processor to execute read and write instructions. In some current computing devices, memory can include static random-access memory (SRAM) that uses bistable latching circuits or flip-flops to store each bit. SRAM may be used as a cache device in a computing device by storing copies of data from slower non-volatile memory. SRAM cells can store single values and any number of SRAM cells can be organized into various columns and rows. In some memory chips, each column of SRAM cells can be connected to a bit circuit and a sense amplifier. In some current sense amplifier designs, sense amplifier circuits are repeated a large number of times within dense memory circuits and contribute to memory efficiency degradation. Cross coupled PFETs (e.g., p-channel field-effect transistors or p-channel metal-oxide semiconductor field-effect transistors) in current sense amplifier designs support high side noise and voltage difference. These may impact density and efficiency of memory arrays.